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INTEGRATED CIRCUITS
DATA SHEET
TZA3005H SDH/SONET STM1/OC3 and STM4/OC12 transceiver
Product specification Supersedes data of 1997 Aug 05 File under Integrated Circuits, IC19 2000 Feb 17
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
FEATURES * Supports STM1/OC3 (155.52 Mbits/s) and STM4/OC12 (622.08 Mbits/s) * Supports reference clock frequencies of 19.44, 38.88, 51.84 and 77.76 MHz * Meets Bellcore, ANSI and ITU-T specifications * Meets ITU jitter specification typically to a factor of 2.5 * Integral high-frequency PLL for clock generation * Interface to TTL logic * Low jitter PECL (Positive Emitter Coupled Logic) interface * 4 or 8-bit STM1/OC3 TTL data path * 4 or 8-bit STM4/OC12 TTL data path * No external filter components required * QFP64 package * Diagnostic and line loopback modes * Lock detect * LOS (Loss of Signal) input * Low power (0.9 W typical) * Selectable frame detection and byte realignment * Loop timing * Forward and reverse clocking * Squelched clock operation * Self-biased PECL inputs to support AC coupling. APPLICATIONS * SDH/SONET modules * SDH/SONET-based transmission systems * SDH/SONET test equipment * ATM (Asynchronous Transfer Mode) over SDH/SONET * Add drop multiplexers * Broadband cross-connects * Section repeaters * Fibre optic test equipment * Fibre optic terminators. ORDERING INFORMATION TYPE NUMBER TZA3005H PACKAGE NAME QFP64 DESCRIPTION plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm GENERAL DESCRIPTION
TZA3005H
The TZA3005H SDH/SONET transceiver chip is a fully integrated serialization/deserialization STM1/OC3 (155.52 Mbits/s) and STM4/OC12 (622.08 Mbits/s) interface device. It performs all necessary serial-to-parallel and parallel-to-serial functions in accordance with SDH/SONET transmission standards. It is suitable for SONET-based applications and can be used in conjunction with the data and clock recovery unit (TZA3004), optical front-end (TZA3023 with TZA3034/44) and a laser driver (TZA3001). A typical network application is shown in Fig.10. A high-frequency phase-locked loop is used for on-chip clock synthesis, which allows a slower external transmit reference clock to be used. A reference clock of 19.44, 38.88, 51.84 or 77.76 MHz can be used to support existing system clocking schemes. The TZA3005H also performs SDH/SONET frame detection. The low jitter PECL interface ensures that Bellcore, ANSI, and ITU-T bit-error rate requirements are satisfied. The TZA3005H is supplied in a compact QFP64 package.
VERSION SOT393-1
2000 Feb 17
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
BLOCK DIAGRAM
TZA3005H
handbook, full pagewidth
LLEN TXPD0 to TXPD7 TXPCLK
31 53 to 60 61 8
TRANSMITTER
D 2 17, 18 TXSD and TXSDQ
8:1 OR 4:1 PARALLEL TO SERIAL
MRST TEST1 TEST2 TEST3 BUSWIDTH
48 10 11 13 30 RF SWITCH BOX
2
21, 20
TXSCLK and TXSCLKQ
(1)
TZA3005H
REFSEL0 and REFSEL1 MODE REFCLK and REFCLKQ SDTTL SDPECL OOF DLEN RXSD and RXSDQ RXSCLK and RXSCLKQ
3, 4 49 15, 14 22 23 33 32 24, 25 27, 28
2 CLOCK SYNTHESIZER 2 CLOCK DIVIDER BY 4 OR BY 8
62 63 64 8 on-chip capacitor 2 1:8 OR 1:4 SERIAL TO PARALLEL 47 35 36, 37, 39, 40, 41, 43 to 45
SYNCLKDIV LOCKDET 19MHZO RXPD0 to RXPD7 RXPCLK FP
2 2
D FRAME HEADER DETECT 52 51 VCC(TXCORE) GNDTXCORE
MGS975
RECEIVER
1 VCC(SYNOUT) GNDSYNOUT DGNDSYN AGNDSYN 2 5 8, 9 6 7 12 GND 16 19 26 29 38, 46 34, 42 GNDRXOUT VCC(RXOUT) GNDRXCORE
VCCD(SYN) VCCA(SYN)
GNDTXOUT
VCC(TXOUT)
VCC(RXCORE)
(1) Dashed lines represent normal operation mode.
Fig.1 Block diagram.
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
PINNING SYMBOL VCC(SYNOUT) GNDSYNOUT REFSEL0 REFSEL1 DGNDSYN VCCD(SYN) VCCA(SYN) AGNDSYN AGNDSYN TEST1 TEST2 GND TEST3 REFCLKQ REFCLK VCC(TXOUT) TXSD TXSDQ GNDTXOUT TXSCLKQ TXSCLK SDTTL SDPECL RXSD RXSDQ VCC(RXCORE) RXSCLK RXSCLKQ GNDRXCORE BUSWIDTH LLEN DLEN OOF GNDRXOUT FP RXPD0 RXPD1 VCC(RXOUT) RXPD2 RXPD3 2000 Feb 17 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 TYPE(1) S G I I G S S G G I I G I I I S O O G O O I I I I S I I G I I I I G O O O S O O ground (synthesizer output) reference clock select input 0 reference clock select input 1 digital ground (synthesizer) digital supply voltage (synthesizer) analog supply voltage (synthesizer) analog ground (synthesizer) analog ground (synthesizer) test and control input test and control input ground test and control input inverted reference clock input reference clock input supply voltage (transmitter output) serial data output inverted serial data output ground (transmitter output) inverted serial clock output serial clock output TTL signal detect input PECL signal detect input serial data input inverted serial data input supply voltage (receiver core) serial clock input inverted serial clock input ground (receiver core) 4/8 bus width select input line loopback enable input (active LOW) diagnostic loopback enable input (active LOW) out-of-frame enable input ground (receiver output) frame pulse output parallel data output 0 parallel data output 1 supply voltage (receiver output) parallel data output 2 parallel data output 3 4 DESCRIPTION supply voltage (synthesizer output)
TZA3005H
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
SYMBOL RXPD4 GNDRXOUT RXPD5 RXPD6 RXPD7 VCC(RXOUT) RXPCLK MRST MODE ALTPIN GNDTXCORE VCC(TXCORE) TXPD0 TXPD1 TXPD2 TXPD3 TXPD4 TXPD5 TXPD6 TXPD7 TXPCLK SYNCLKDIV LOCKDET 19MHZO Note 1. Pin type abbreviations: O = Output, I = Input, S = Supply, G = Ground. PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 TYPE(1) O G O O O S O I I I G S I I I I I I I I I O O O parallel data output 4 ground (receiver output) parallel data output 5 parallel data output 6 parallel data output 7 supply voltage (receiver output) receive parallel clock output master reset (active LOW) serial data rate select STM1/STM4 test and control input ground (transmitter core) supply voltage (transmitter core) parallel data input 0 parallel data input 1 parallel data input 2 parallel data input 3 parallel data input 4 parallel data input 5 parallel data input 6 parallel data input 7 transmit parallel clock input transmit byte/nibble clock output (synchronous) lock detect output 19 MHz reference clock output DESCRIPTION
TZA3005H
2000 Feb 17
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
TZA3005H
51 GNDTXCORE
handbook, full pagewidth
52 VCC(TXCORE)
62 SYNCLKDIV
63 LOCKDET
64 19MHZO
61 TXPCLK
50 ALTPIN
60 TXPD7
59 TXPD6
58 TXPD5
57 TXPD4
56 TXPD3
55 TXPD2
54 TXPD1
53 TXPD0
VCC(SYNOUT) 1 GNDSYNOUT REFSEL0 REFSEL1 DGNDSYN VCCD(SYN) VCCA(SYN) AGNDSYN AGNDSYN 2 3 4 5 6 7 8
49 MODE
48 MRST 47 RXPCLK 46 VCC(RXOUT) 45 RXPD7 44 RXPD6 43 RXPD5 42 GNDRXOUT 41 RXPD4
TZA3005H
9 40 RXPD3 39 RXPD2 38 VCC(RXOUT) 37 RXPD1 36 RXPD0 35 FP 34 GNDRXOUT 33 OOF TXSCLKQ 20 TXSCLK 21 SDTTL 22 SDPECL 23 RXSD 24 RXSDQ 25 VCC(RXCORE) 26 RXSCLK 27 RXSCLKQ 28 GNDRXCORE 29 BUSWIDTH 30 LLEN 31 TXSDQ 18 GNDTXOUT 19 DLEN 32 TXSD 17
TEST1 10 TEST2 11 GND 12 TEST3 13 REFCLKQ 14 REFCLK 15 VCC(TXOUT) 16
MGK483
Fig.2 Pin configuration.
2000 Feb 17
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
FUNCTIONAL DESCRIPTION Introduction The TZA3005H transceiver implements SDH/SONET serialization/deserialization, transmission and frame detection/recovery functions. The TZA3005H can be used as the front-end for SONET equipment. It handles the serial receive and transmit interface functions including parallel-to-serial and serial-to-parallel conversion and clock generation. A block diagram showing the basic operation of the chip is shown in Fig.1. The TZA3005H has a transmitter section, a receiver section, and an RF switch box. The sequence of operations is as follows: * Transmitter operations: - 4 or 8-bit parallel input - parallel-to-serial conversion - serial output. * Receiver operations: - serial input - frame detection - serial-to-parallel conversion - 4 or 8-bit parallel output. The RF switch box receives serial clock and data signals from the transmitter section, the receiver input buffers and from the clock synthesizer. These signals are routed by multiplexers to the transmitter section, the transmitter output, the receiver and to the clock divider, depending on the status of the control inputs. The switch box also supports a number of test and loop modes. Transmitter operation The transmitter section of the TZA3005H converts STM1/OC3 or STM4/OC12 byte-serial input data to a bit-serial output data format. Input data rates of 19.44, 38.88, 77.76 or 155.52 Mbytes/s are converted to an output data rate of either 155.52 or 622.08 Mbits/s. It also provides diagnostic loopback (transmitter to receiver), line loopback (receiver to transmitter) and also loop timing (transmitter clocked by the receiver clock). An integral frequency synthesizer, comprising a phase-locked loop and a divider, can be used to generate a high-frequency bit clock from an input reference clock frequency of 19.44, 38.88, 51.84 or 77.76 MHz. REFSEL1 0 0 1 1 REFSEL0 0 1 0 1 CLOCK SYNTHESIZER
TZA3005H
The clock synthesizer generates a serial output clock (TXSCLK) which is phase synchronised with the input reference clock (REFCLK). The serial output clock is synthesized from one of four SDH/SONET input reference clock frequencies and can have a frequency of either 155.52 MHz for STM1/OC3 or 622.08 MHz for STM4/OC12 selected by the MODE input (see Table 1). Table 1 Transmitter output clock (TXSCLK) frequency options TXSCLK FREQUENCY 155.52 MHz 622.08 MHz OPERATING MODE STM1/OC3 STM4/OC12
MODE INPUT 0 1
The frequency of the input reference clock is divided to obtain a frequency of about 19 MHz which is fed to the phase detector in the PLL. The appropriate divisor is selected by control inputs REFSEL0 and REFSEL1 as shown in Table 2. Table 2 Reference frequency (REFCLK) options REFCLK FREQUENCY 19.44 MHz 38.88 MHz 51.84 MHz 77.76 MHz
To ensure the TXSCLK frequency is accurate enough to operate in a SONET system, REFCLK must be generated from a differential PECL crystal oscillator having a frequency accuracy better than 4.6 ppm for compliance with "ITU G.813 (option 1)", or 20 ppm for "ITU G.813 (option 2)". To comply with SONET jitter requirements, the maximum value specified for reference clock signal jitter must be guaranteed over the 12 kHz to 1 MHz bandwidth (see Table 3).
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
Table 3 ITU reference clock signal (REFCLK) jitter limits OPERATING MODE STM1/OC3 STM4/OC12 FRAME AND BYTE BOUNDARY DETECTION The on-chip PLL contains a phase detector, a loop filter and a VCO. The phase detector compares the phases of the VCO and the divided REFCLK signals. The loop filter converts the phase detector output to a smooth DC voltage which controls the VCO frequency and ensures that it is always 622.08 MHz. In STM1/OC3 mode, the correct output frequency at TXSCLK is obtained by dividing the VCO frequency by 4. The loop filter parameters are optimized for minimal output jitter.
CLOCK DIVIDER
TZA3005H
MAXIMUM JITTER OF REFCLK 12 kHz TO 1 MHz 56 ps (RMS) 14 ps (RMS)
mode, a 4-bit parallel data stream is generated having a clock frequency of either 38.88 or 155.52 MHz. It also provides diagnostic loopback (transmitter to receiver), line loopback (receiver to transmitter) and squelched clock operation (transmitter clock to receiver).
The clock divider generates either a byte rate or a nibble rate version of the serial output clock (TXSCLK) which is output on pin SYNCLKDIV (see Table 4). Table 4 MODE INPUT 0 0 1 1 SYNCLKDIV frequency BUSWIDTH 0 (nibble) 1 (byte) 0 (nibble) 1 (byte) SYNCLKDIV FREQUENCY 38.88 MHz 19.44 MHz 155.52 MHz 77.76 MHz OPERATING MODE STM1/OC3 STM1/OC3 STM4/OC12 STM4/OC12
The frame and byte boundary detection circuit searches the incoming data for the correct 48-bit frame pattern which is a sequence of three consecutive A1 bytes of F0 H followed immediately by three consecutive A2 bytes of 28 H. Frame pattern detection is enabled and disabled by the out-of-frame enable input (OOF). Detection is enabled by a rising edge on pin OOF, and remains enabled while the level on pin OOF is HIGH. It is disabled when at least one frame pattern is detected and the level on pin OOF is no longer HIGH. When frame pattern detection is enabled, the frame pattern is used to locate byte and frame boundaries in the incoming data stream (Received Serial Data (RXSD) or looped transmitter data). The serial to parallel converter block uses the located byte boundary to divide the incoming data stream into bytes for output on the parallel output data bus (RXPD0 to RXPD7). When the correct 48-bit frame pattern is detected, the occurrence of the frame boundary is indicated by the Frame Pulse (FP) signal. When frame pattern detection is disabled, the byte boundary is fixed, and only frame patterns which align with the fixed byte boundary produce an output on pin FP. It is extremely unlikely that random data in an STM1/OC3 or STM4/OC12 data stream will replicate the 48-bit frame pattern. Therefore, the time taken to detect the beginning of the frame should be less than 250 s (as specified in "ITU G.783") even at extremely high bit error rates. Once down-stream overhead circuits verify that frame and byte synchronization are correct, OOF can be set LOW to prevent the frame search process synchronizing to a mimic frame pattern. SERIAL-TO-PARALLEL CONVERTER The serial-to-parallel converter causes a delay between the first bit of an incoming serial data byte to the start of the parallel output of that byte. The delay depends on the time taken for the internal parallel load timing circuit to synchronize the data byte boundaries to the falling edge of RXPCLK. The timing of RXPCLK is independent of the byte boundaries. RXPCLK is neither truncated nor extended during reframe sequences.
SYNCLKDIV is intended for use as a byte speed clock for upstream multiplexing and overhead processing circuits. Using SYNCLKDIV for upstream circuits ensures a stable frequency and phase relationship is maintained between the data in to and out of the TZA3005H. For parallel-to-serial data conversion, the parallel input data is transferred from the TXPCLK byte clock timing domain to the internally generated bit clock timing domain. The internally generated bit clock does not have to be phase aligned to the TXPCLK signal but must be synchronized by the master reset (MRST) signal. Receiver operation The receiver section of the TZA3005H converts STM1/OC3 or STM4/OC12 bit-serial input data to a parallel data output format. In byte mode, input data rates of 155.52 or 622.08 Mbits/s are converted to an output data rate of either 19.44 or 77.76 Mbytes/s. In nibble 2000 Feb 17 8
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
Transceiver pin descriptions TRANSMITTER INPUT SIGNALS
TZA3005H
Signal detect PECL (SDPECL)
This is a single-ended PECL input with an internal pull-down resistor. This input is driven by an external optical receiver module to indicate a loss of received optical power (LOS). SDPECL is active HIGH when SDTTL is at logic 0 and active LOW when SDTTL is at logic 1or unconnected. When there is a loss of signal, SDPECL is inactive and the bit-serial data on pins RXSD and RXSDQ is internally forced to a constant zero. When SDPECL is active, the bit-serial data on pins RXSD and RXSDQ is processed normally (see Table 5).
Parallel data inputs (TXPD0 to TXPD7)
These are TTL data word inputs. The input data is aligned with the TXPCLK parallel input clock. TXPD7 is the most significant bit (corresponding to bit 1 of each PCM word, the first bit transmitted). TXPD0 is the least significant bit (corresponding to bit 8 of each PCM word, the last bit transmitted). Bits TXPD0 to TXPD7 are sampled on the rising edge of TXPCLK. If a 4-bit bus width is selected, TXPD7 is the most significant bit and TXPD4 is the least significant bit. Inputs TXPD0 to TXPD3 are unused.
Signal detect TTL (SDTTL)
This is a single-ended TTL input with an internal pull-up resistor. This input is driven by an external optical receiver module to indicate a loss of received optical power (LOS). SDTTL is active HIGH when pin SDPECL is logic 0 or unconnected, and active LOW when pin SDPECL is at logic 1. When there is a loss of signal, SDTTL is inactive and the bit-serial data on pins RXSD and RXSDQ is internally forced to a constant zero. When SDTTL is active, the bit-serial data on pins RXSD and RXSDQ is processed normally (see Table 5). If pin SDTTL instead of pin SDPECL is to be connected to the optical receiver module, connect pin SDPECL to a logic HIGH-level to implement an active-LOW signal detect, or leave pin SDPECL unconnected to implement an active-HIGH signal detect. Table 5 SDPECL/SDTTL truth table SDTTL 0 1 or floating 0 1 or floating RXPD OUTPUT DATA 0 RXSD input data RXSD input data 0
Parallel clock input (TXPCLK)
This is a TTL input clock signal having a frequency of either 19.44, 38.88, 77.76 or 155.52 MHz and a duty factor of nominally 50%, to which input data bits TXPD0 to TXPD7 are aligned. TXPCLK transfers the input data to a holding register in the parallel-to-serial converter. The rising edge of TXPCLK samples bits TXPD0 to TXPD7. After a master reset, one rising edge of TXPCLK is required to fully initialize the internal data path. RECEIVER INPUT SIGNALS
Receive serial data (RXSD and RXSDQ)
These are differential PECL serial data inputs, normally connected to an optical receiver module or to the TZA3004 data and clock recovery unit, and clocked by RXSCLK and RXSCLKQ. These inputs can be AC coupled without external biasing.
SDPECL 0 or floating 0 or floating 1 1
Receive serial clock (RXSCLK and RXSCLKQ)
These are differential PECL recovered clock signals synchronized to the input data RXSD and RXSDQ. It is used by the receiver as the master clock for framing and deserialization functions. These inputs can be AC coupled without external biasing.
COMMON INPUT SIGNALS
Out-of-frame (OOF)
This is a TTL signal which enables frame pattern detection logic in the TZA3005H. The frame pattern detection logic is enabled by a rising edge on pin OOF, and remains enabled until a frame boundary is detected and OOF goes LOW. OOF is an asynchronous signal with a minimum pulse width of one RXPCLK period (see Fig.3).
Bus width selection (BUSWIDTH)
This is a TTL signal which selects 4-bit or 8-bit operation for the transmit and receive parallel interfaces. BUSWIDTH LOW selects a 4-bit bus width. BUSWIDTH HIGH selects an 8-bit bus width.
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
Reference clock (REFCLK and REFCLKQ)
These are differential PECL reference clock inputs for the internal bit clock synthesizer.
TZA3005H
Parallel clock (SYNCLKDIV)
This is a TTL reference clock generated by dividing the internal bit clock by eight, or by four when BUSWIDTH is LOW. It is normally used to coordinate byte-wide transfers between upstream logic and the TZA3005H.
Diagnostic loopback enable (DLEN)
This is an active-LOW TTL signal which selects diagnostic loopback. When DLEN is HIGH, the TZA3005H receiver uses the primary data (RXSD) and clock (RXSCLK) inputs. When DLEN is LOW, the receiver uses the diagnostic loopback clock and the transmitter input data.
Lock detect (LOCKDET)
This is an active HIGH CMOS signal. When active, it indicates that the transmit PLL is locked to the reference clock input.
Master reset (MRST)
This is an active LOW TTL signal which initializes the transmitter. SYNCLKDIV is LOW during reset.
19 MHz clock output (19MHZO)
This is a 19 MHz CMOS clock from the clock synthesizer. It can be connected to the reference clock input of an external clock recovery unit, such as the TZA3004. RECEIVER OUTPUT SIGNALS
Line loopback enable (LLEN)
This is an active LOW TTL signal which selects line loopback. When LLEN is LOW, the TZA3005H routes the data and clock from the receiver inputs RXSD and RXSCLK to the transmitter outputs TXSD and TXSCLK.
Parallel data outputs (RXPD0 to RXPD7)
These outputs comprise a parallel TTL data bus. The parallel output data is aligned with the parallel output clock (RXPCLK). RXPD7 is the most significant bit (corresponding to bit 1 of each PCM word, the first bit received). RXPD0 is the least significant bit (corresponding to bit 8 of each PCM word, the last bit received). RXPD0 to RXPD7 are updated on the falling edge of RXPCLK. When a 4-bit bus width is selected, RXPD7 is the most significant bit and bit 4 is the least significant bit. Outputs RXPD0 to RXPD3 are forced LOW.
Reference select (REFSEL0 and REFSEL1)
These are TTL signals which select the reference clock frequency (see Table 2).
Mode select (MODE)
This TTL signal selects the transmitter serial data rate. MODE LOW selects 155.52 Mbits/s. MODE HIGH selects 622.08 Mbits/s.
Frame pulse (FP)
This is a TTL signal which indicates frame boundaries detected in the incoming data stream on pin RXSD. When frame pattern detection is enabled (see Section "Out-of-frame (OOF)"), FP goes HIGH for one cycle of RXPCLK when a 48-bit sequence matching the frame pattern is detected on inputs RXSD and RXSDQ. When frame pattern detection is disabled, FP goes HIGH only when the incoming data matches the frame pattern and fits exactly within the fixed byte boundary. FP is updated on the falling edge of RXPCLK.
Test inputs (ALTPIN, TEST1, TEST2, TEST3)
These are active HIGH TTL signals which control the operating mode and test internal circuits during production testing. For normal operation, these inputs are left unconnected and internal pull-down resistors hold each pin LOW. See Table 7 for more details. TRANSMITTER OUTPUT SIGNALS
Transmit clock outputs (TXSCLK and TXSCLKQ)
These are differential PECL serial clock signals which can be used to retime TXSD. The clock frequency is either 155.52 MHz or 622.08 MHz depending on the operating mode.
Parallel output clock (RXPCLK)
This is a TTL byte-rate output clock having a frequency of either 19.44, 38.88, 77.76 or 155.52 MHz and a duty factor of nominally 50%, to which the byte-serial output data bits RXPD0 to RXPD7 are aligned. The falling edge of RXPCLK updates the data on pins RXPD0 to RXPD7 and the FP signal.
Transmit serial data (TXSD and TXSDQ)
These are differential PECL serial data stream outputs which are normally connected to an optical transmitter module or to the TZA3001 laser driver. 2000 Feb 17 10
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
Other operating modes DIAGNOSTIC LOOPBACK A transmitter-to-receiver loopback mode is available for diagnostic purposes. When DLEN is LOW, the differential serial clock and data from the transmitter parallel-to-serial block continue to be routed to transmitter outputs, but are also routed to the receiver serial-to-parallel block instead of the receiver input signals from pins RXSD/RXSDQ and RXSCLK/RXSCLKQ. LINE LOOPBACK A receiver-to-transmitter loopback mode is available for line testing purposes. When LLEN is LOW, the receiver input signals (RXSD/RXSDQ and RXSCLK/RXSCLKQ) are routed, after retiming, to the transmitter output buffers. The receiver clock and data are also routed to the serial-to-parallel block. LOOP TIMING In loop timing mode, the transmitter section is clocked by the receiver input clock (RXSCLK) instead of by the internal clock synthesizer. SYNCLKDIV is now derived from RXSCLK so that it can be used to clock upstream transmitter logic. Loop timing is enabled by setting pins ALTPIN, TEST1, TEST2 and TEST3 (see Table 6). After activating the loop timing mode, the receiver clock must be synchronized to the transmitter input data (TXPD0 to TXPD7) by activating master reset (MRST). In loop timing mode, the internal clock synthesizer is still used to generate the 19MHz output clock signal on pin 19MHZO. SQUELCHED CLOCK OPERATION
TZA3005H
Some clock recovery devices force their recovered output clock to zero if a loss of input signal is detected. If this happens, the SDTTL or SDPECL signals are inactive and no clock signal is present at pins RXSCLK and RXSCLKQ. If no clock signal is present at pins RXSCLK/RXSCLKQ, there is no RXPCLK signal. This may not be suitable for some applications, in which case, the TZA3005H can be set to squelched clock operation by setting pins ALTPIN, TEST1, TEST2 and TEST3 as shown in Table 6. In squelched clock operation, receiver timing is performed by a part of the internal clock synthesizer which normally only provides transmitter timing. This produces a RXPCLK clock signal when either SDTTL or SDPECL is inactive. If either SDTTL or SDPECL is inactive in squelched clock operation, it is equivalent to normal operation. During a transition from normal operation to squelched clock operation, the RXPCLK clock cycle exhibits a once-only random shortening. Table 6 shows that the same operating mode can be selected at different settings of the control inputs. If ALTPIN = 0, the STM4 nibble mode is not available, but is used for squelched clock operation. If ALTPIN = 1, all operating modes are available, including STM4 nibble mode.
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
Table 6 Truth table operating modes BUSWIDTH (pin 30) X 0 MODE (pin 49) 0 1 SD(1) X 0 LLEN DLEN (pin 31) (pin 32) 1 1 1 1
TZA3005H
ALTPIN TEST1 TEST2 TEST3 (pin 50) (pin 10) (pin 11) (pin 13) 0 0 X X X X 0 0
FUNCTIONAL OPERATING MODE normal operation (STM1 byte/nibble) squelched clock operation (STM4 byte) normal operation (STM4 byte) normal operation (STM4 byte) loop timing normal operation loop timing squelched clock operation normal operation diagnostic loopback line loopback
0 0 0 1 1 1 1 X X Note
X X X 0 0 0 0 X X
X X X 0 0 1 1 X X
0 0 1 0 1 0 0 X X
0 1 X X X X X X X
1 1 X X X X X X X
1 X X X X 0 1 X X
1 1 1 1 1 1 1 X 0
1 1 1 1 1 1 1 0 X
1. SD denotes either pin 22 (SDTTL) or pin 23 (SDPECL) (signal present = active = 1; loss of signal = inactive = 0). During a loss of signal, the outputs RXPD0 to RXPD7 are forced to zero (see Table 5). Receiver frame alignment Figure 3 shows a typical frame and boundary alignment sequence. Frame and byte boundary detection is enabled on the rising edge of OOF and remains enabled while OOF is HIGH. Byte boundaries are recognized after the third A2 byte is received. FP goes HIGH for one RXPCLK cycle to indicate that this is the first data byte with the correct byte alignment on the output parallel data bus (RXPD0 to RXPD7). When interfaced with a section terminating device, OOF must remain HIGH for a full frame period after the initial frame pulse (FP). This is to allow the section terminating device to internally verify that frame and byte alignment are correct (see Fig.4). Because at least one frame pattern will have been detected since the rising edge of OOF, boundary detection is disabled when OOF goes LOW. The frame and byte boundary detection block is activated on the rising edge of OOF, and remains active until a frame pulse (FP) occurs and OOF goes LOW, whichever occurs last. Figure 4 shows a typical OOF timing pattern when the TZA3005H is connected to a down stream section terminating device. OOF stays HIGH for one full frame after the first frame pulse (FP). The frame and byte boundary detection block is active until OOF goes LOW. Figure 5 shows frame and byte boundary detection activated on the rising edge of OOF, and deactivated by the first frame pulse (FP) after OOF goes LOW.
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
TZA3005H
handbook, full pagewidth RXSCLK
OOF
RXSD A1 A1 A1 A2 A2 A2
RXPD0 to RXPD7 invalid data
A2 (28H) valid data
RXPCLK
FP
MGK485
Fig.3 Frame and byte detection.
handbook, halfpage
boundary detection enabled
handbook, halfpage
boundary detection enabled
OOF OOF FP FP
MGK486 MGK487
Fig.4
OOF operating time with PM5312 STTX or PM5355 SUNI-622 (see Table 7).
Fig.5 Alternate OOF timing.
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Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VCC Vn supply voltage voltage on any input pin between two differential PECL input pins on SDPECL input pin II(n) current into any TTL output pin into any PECL output pin Ptot Tstg Tj(bias) Tcase(bias) HANDLING total power dissipation storage temperature junction temperature under bias case temperature under bias -8 -50 - -65 -55 -55 +8 +1.5 1.5 +150 +125 +100 -0.5 -2 VCC - 3 PARAMETER MIN. -0.5 +6
TZA3005H
MAX. V V V V
UNIT
VCC + 0.5 +2 VCC + 0.5
mA mA W C C C
Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take normal precautions appropriate to handling MOS devices (see "Handling MOS devices"). THERMAL CHARACTERISTICS SYMBOL Tamb Tj Rth(j-a) Notes 1. For applications with Tamb >75 C, it is advised that the board layout is designed to allow optimum heat transer. 2. Rth(j-a) is determined with the IC soldered on a standard single-sided 57 x 57 x 1.6 mm FR4 epoxy PCB with 35 m thick copper tracks. The measurements are performed in still air. This value will vary depending on the number of board layers, copper sheet thickness and area, and the proximity of surrounding components. ambient temperature; note 1 junction temperature thermal resistance from junction to ambient; note 2 PARAMETER VALUE -40 -40 55 UNIT +85 +125 K/W
2000 Feb 17
14
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
TZA3005H
DC CHARACTERISTICS For typical values, Tamb = 25 C and VCC = 3.3 V; minimum and maximum values are valid over entire Tj and VCC ranges. SYMBOL General VCC Ptot supply voltage total power dissipation outputs open; VCC = 3.47 V VCC = 5.5 V ICC(tot) total supply current outputs open; VCC = 3.47 V VCC = 5.5 V TTL inputs VIH VIL IIH IIL Rpu Rpd HIGH-level input voltage LOW-level input voltage HIGH-level input current LOW-level input current pull-up resistor pull-down resistor at pin SDTTL IOH = -1 mA; note 3 IOL = 4 mA note 4 terminated with 50 to VCC - 2.0 V PECL inputs are AC coupled VIH = VCC; note 1 VIL = 0; note 1 note 2 2 0 -10 -10 8 8 - - - - 10 10 VCC 0.8 +10 +10 12 12 V V A A k k - - 272 - 394 420 mA mA - - 0.9 - 1.4 2.3 W W 3.0 3.3 5.5 V PARAMETER CONDITION MIN. TYP. MAX. UNIT
TTL outputs VOH VOL PECL I/O VIH VIL VOH VOL Vo(dif) HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage differential output voltage VCC - 1.2 - VCC - 1.1 VCC - 1.9 600 100 - - - - - - - VCC - 1.6 VCC - 0.9 VCC - 1.6 900 - V V V V mV mV HIGH-level output voltage LOW-level output voltage 2.4 - - - - +0.5 V V
Vi(dif)(sens) differential input sensitivity Notes
1. For input pins REFSEL0, REFSEL1, BUSWIDTH, LLEN, DLEN, OOF, MRST, MODE, TXPDn, TXPCLK. 2. For input pins SDPECL, ALTPIN, TEST1, TEST2, TEST3. 3. Only applies to pin 19MHZO; guaranteed by simulation. 4. The PECL inputs are high impedance. The transmission lines should be terminated externally using an appropriate termination.
2000 Feb 17
15
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
TZA3005H
AC CHARACTERISTICS For typical values, Tamb = 25 C and VCC = 3.3 V; minimum and maximum values are valid over entire Tj and VCC ranges. SYMBOL General fTXSCLK(nom) nominal TXSCLK frequency fREFCLK as Table 2; MODE = 0 MODE = 1 Jo fREFCLK(tol) data output jitter in lock; note 1 frequency tolerance of REFCLK meets SONET output frequency specification; note 1 rise/fall time PECL outputs 20% to 80%; 50 load to VCC - 2.0 V 155.517 622.068 - -20 155.52 622.08 0.004 - 155.523 622.092 0.006 +20 MHz MHz UI (RMS) ppm PARAMETER CONDITION MIN. TYP. MAX. UNIT
tr, tf
-
220
450
ps
Receiver timing (see Figs 6 and 7) CL RXPCLK tPD tsu th TTL output load capacitance duty factor of RXPCLK propagation delay; RXPCLK LOW to RXPDn, FP set-up time; RXSD/RXSDQ to RXSCLK/RXSCLKQ hold time; RXSD/RXSDQ to RXSCLK/RXSCLKQ note 2 - 40 -0.5 400 400 - 50 +1.5 - - 15 60 +2.5 - - pF % ns ps ps
Transmitter timing (see Figs 8 and 9) TXSCLK tsu th tPD Notes 1. Jitter on pins REFCLK/REFCLKQ complies with Table 3. 2. Minimum value is 35% in STM4 nibble mode. duty factor of TXSCLK set-up time; TXPDn to TXPCLK hold time; TXPDn to TXPCLK propagation delay time; TXSCLK LOW to TXSD 40 -0.5 1.5 - 50 - - - 60 - - 440 % ns ns ps
2000 Feb 17
16
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
TZA3005H
handbook, halfpage
RXPCLK
handbook, halfpage
RXSCLK
t PD RXPD0 to RXPD7, FP
MGK488
tsu RXSD/RXSDQ
th
MGK489
For TTL outputs, tPD is the time (ns) from the 50% point of the reference signal to the 50% point of the output signal.
Timing is measured from the cross-over point of the reference signal to the cross-over point of the input signal.
Fig.6 Receiver output timing.
Fig.7 Receiver input timing.
handbook, halfpage
TXPCLK
handbook, halfpage
TXSCLK tsu TXPD0 to TXPD7
MGK490 MGK491
th t PD TXSD
For TTL signals, tsu between input data and clock signals is the time (ps) from the 50% point of the data to the 50% point of the clock. For TTL signals, th between input data and clock signals is the time (ps) from the 50% point of the clock to the 50% point of the data.
Timing is measured from the cross-over point of the reference signal to the cross-over point of the output signal.
Fig.8 Transmitter input timing.
Fig.9 Transmitter output timing.
2000 Feb 17
17
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
INTERNAL CIRCUITRY PIN 24 27 25 28 SYMBOL AND DESCRIPTION RXSD; serial data input RXSCLK; serial clock input RXSDQ; inverted serial data input RXSCLKQ; inverted serial clock input
24, 27 10 k
TZA3005H
CHARACTERISTIC PECL inputs
handbook, halfpage
EQUIVALENT CIRCUIT
VCC -1.35 V 10 k 25, 28
100 A GND
MGS979
14 15
REFCLKQ; inverted reference clock input REFCLK; reference clock input
PECL inputs
handbook, halfpage
VCC -1.35 V VCC 600 fF VCC 600 fF 2 k 15 10 k
10 k
2 k 14
100 A GND
MGS980
23
SDPECL; PECL signal detect input
PECL input
handbook, halfpage
VCC 600 fF 25 k VCC -1.35 V
23
100 A GND
MGS981
2000 Feb 17
18
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
PIN 3 4 10 11 13 30 31 32 33 48 49 50 22 53 54 55 56 57 58 59 60 61 36 37 39 40 41 43 44 45 47 62 SYMBOL AND DESCRIPTION REFSEL0; reference clock select input 0 REFSEL1; reference clock select input 1 TEST1; test and control input TEST2; test and control input TEST3; test and control input BUSWIDTH; 4/8 bus width select input LLEN; line loopback enable input (active LOW) DLEN; diagnostic loopback enable input (active LOW) OOF; out-of-frame enable input MRST; master reset (active LOW) MODE; serial data rate select STM1/STM4 ALTPIN; test and control input SDTTL; TTL signal detect input TXPD0; parallel data input 0 TXPD1; parallel data input 1 TXPD2; parallel data input 2 TXPD3; parallel data input 3 TXPD4; parallel data input 4 TXPD5; parallel data input 5 TXPD6; parallel data input 6 TXPD7; parallel data input 7 TXPCLK; transmit parallel clock input RXPD0; parallel data output 0 RXPD1; parallel data output 1 RXPD2; parallel data output 2 RXPD3; parallel data output 3 RXPD4; parallel data output 4 RXPD5; parallel data output 5 RXPD6; parallel data output 6 RXPD7; parallel data output 7 RXPCLK; receive parallel clock output SYNCLKDIV; transmit byte/nibble clock output (synchronous) 19
GND
MGS984
TZA3005H
CHARACTERISTIC TTL inputs
handbook, halfpage
EQUIVALENT CIRCUIT
3, 4, 10, 11, 13, 30 to 33, 48 to 50
50 k
1 pF GND
MGS982
TTL inputs
handbook, halfpage
22, 53 to 61
100
50 A
GND
MGS983
TTL outputs
handbook, halfpage
VCC
15 36, 37, 39 to 41, 43 to 45, 47, 62 15
2000 Feb 17
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
PIN 63 64 SYMBOL AND DESCRIPTION LOCKDET; lock detect output; R = 50 19MHZO; 19 MHz reference clock output; R = 20 CHARACTERISTIC CMOS outputs
handbook, halfpage
TZA3005H
EQUIVALENT CIRCUIT
VCC
50 63, 64
R
GND
MGS985
17 18 20 21
TXSD; serial data output TXSDQ; inverted serial data output TXSCLKQ; inverted serial clock output TXSCLK; serial clock output
PECL outputs
handbook, halfpage VCC
17, 21 18, 20 500 A 500 A GND
MGS986
2000 Feb 17
20
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TZA3001
8 LASER DRIVER LASER DIODE
APPLICATION INFORMATION
Philips Semiconductors
optical fibre
handbook, full pagewidth
PHOTO DIODE
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
TZA3023
AND
TZA3044
OPTICAL RECEIVER
TZA3004 data
DCR(1) clock 8
TZA3005
clock
TZA3005
CONTROLLER TRANSCEIVER 8
21
CONTROLLER 8 TRANSCEIVER
TZA3023 TZA3004
data DCR(1) AND
PHOTO DIODE
LASER DIODE
TZA3044
OPTICAL RECEIVER
TZA3001
LASER DRIVER
MGK494
Product specification
TZA3005H
(1) DCR = Data and Clock Recovery unit.
Fig.10 Application diagram.
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
Forward clocking It is sometimes necessary to `forward clock' data in an SDH/SONET system. When this is the case, the input parallel data clock (TXPCLK) and the reference clock (REFCLK/REFCLKQ) from which the high speed serial clock is synthesized will both originate from the same clock source. This section explains how to configure the TZA3005H to operate in this mode. The connections required for forward clocking are shown in Fig.13. There are no timing specifications for the phase relationship between REFCLK and TXPCLK. The TZA3005H can handle any phase relationship between these two input clocks if they are derived from the same clock source. The TZA3005H internal transmitter logic must be synchronized by asserting a master reset (MRST). Reverse clocking
TZA3005H
In many cases, a reverse clocking scheme is used where the upstream logic is clocked by the TZA3005H using SYNCLKDIV (see Fig.14). There is no requirement specification for the propagation delay from SYNCLKDIV to TXPCLK because the TZA3005H can handle any phase relationship between these two signals. The TZA3005H internal transmitter logic must be synchronized by asserting a master reset (MRST). PECL output termination The PECL outputs have to be terminated with 50 connected to VCC - 2.0 V. If this voltage is not available, a Thevenin termination can be used as shown in Figs 11 and 12.
handbook, halfpage
VCC = 5.0 V R1 83.3 R2 83.3 TXSD/TXSCLK TXSDQ/TXSCLKQ R3 125 GND R4 125
MGK654
handbook, halfpage
VCC = 3.3 V R1 127 R2 127 TXSD/TXSCLK TXSDQ/TXSCLKQ R3 82.5 R4 82.5
MGS978
GND
Fig.11 PECL output termination scheme (VCC = 5.0 V).
Fig.12 PECL output termination scheme (VCC = 3.3 V).
2000 Feb 17
22
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
TZA3005H
handbook, full pagewidth
CLOCK SOURCE
PECL
REFCLK TXPCLK ASIC 8 parallel data
TZA3005
TXPD0 to TXPD7
serial data
MGS976
Fig.13 TZA3005H in forward clocking scheme.
handbook, full pagewidth
CLOCK SOURCE
PECL
REFCLK TXPCLK ASIC 8 parallel data
TZA3005
TXPD0 to TXPD7 SYNCLKDIV
MGS977
serial data
Fig.14 TZA3005H in reverse clocking scheme.
2000 Feb 17
23
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
Table 7 Suggested interface devices MANUFACTURER Philips TYPE TZA3004 TZA3031/3001 TZA3034/3044 TZA3033/3023 PMC-Sierra PM5312 PM5355 DATA RATE (Mbits/s) 622 or 155 155/622 155/622 155/622 155 or 622 622 laser driver post amplifier
TZA3005H
FUNCTION clock recovery
transimpedance amplifier transport terminal transceiver Saturn user network interface
2000 Feb 17
24
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm
TZA3005H
SOT393-1
c
y X
A 48 49 33 32 ZE
e E HE wM pin 1 index 64 1 bp D HD wM ZD B vM B 16 vMA 17 bp Lp L detail X A A2 A1 (A 3)
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.00 A1 0.25 0.10 A2 2.75 2.55 A3 0.25 bp 0.45 0.30 c 0.23 0.13 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.8 HD HE L Lp 1.03 0.73 v 0.16 w 0.16 y 0.10 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o
o
17.45 17.45 1.60 16.95 16.95
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT393-1 REFERENCES IEC 134E07 JEDEC MS-022 EIAJ EUROPEAN PROJECTION
ISSUE DATE 99-12-27 00-01-19
2000 Feb 17
25
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
TZA3005H
* For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2000 Feb 17
26
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12 transceiver
Suitability of surface mount IC packages for wave and reflow soldering methods
TZA3005H
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
2000 Feb 17
27
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403510/150/02/pp28
Date of release: 2000
Feb 17
Document order number:
9397 750 06573

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